1. Field of the Invention
This invention relates to drive circuits suitable for driving various digital circuits with a clock signal. More particularly, but not exclusively, the invention relates to drive circuits suitable for driving a frame transfer type charge coupled device (CCD) with a clock signal.
2. Description of the Prior Art
Recently, television cameras have come into use in which a CCD is utilized as a pick-up member or image sensor thereof. Since a CCD needs a clock signal in order to transfer the charges accumulated therein, a drive circuit such as that shown in FIG. 1 of the accompanying drawings has been used to drive the CCD with a clock signal. Such a drive circuit has to provide a clock signal of high frequency and to supply the clock signal to a supply terminal of the CCD which presents a large capacitance.
In the prior art drive circuit shown in FIG. 1, coupling capacitors C.sub.1 and C.sub.2 are charged and discharged to cause transistors Q.sub.1 and Q.sub.2 to be made ON alternately. Therefore, a driving clock signal can be derived from an output terminal OUT and then fed to the CCD (not shown). In this case, diodes D.sub.1 and D.sub.2 are used to perform the charging and discharging of the coupling capacitors C.sub.1 and C.sub.2 thereby to prevent the transistors Q.sub.1 and Q.sub.2 from being damaged.
However, this drive circuit has the inherent defect that the transistors Q.sub.1 and Q.sub.2 can be made ON only during the period when the coupling capacitors C.sub.1 and C.sub.2 are being charged, and it is impossible to prolong the duration of this period unless the capacitances of the coupling capacitors C.sub.1 and C.sub.2 are sufficiently large.
FIG. 2 of the accompanying drawings shows a prior art CCD, of the so-called frame transfer type, comprising a photosensitive image pick-up section 1, an accumulation or storage section 2, and a read-out register 3 respectively located as illustrated. In use of this CCD four suitably phased clock signals .0..sub.I1 to .0..sub.I4 are applied to the image pick-up section 1, four suitably phased clock signals .0..sub.S1 to .0..sub.S4 are applied to the storage section 2, and four suitably phased clock signals .0..sub.R1 to .0..sub.R4 are applied to the read-out register 3 to effect serial read-out via an amplifier 4. When such a frame transfer type CCD is employed, it is necessary to use clock signals, as shown in FIG. 3 of the accompanying drawings, having quite a long stop interval T corresponding to the photosensitive time, and also a pulse interval (pulse width t) which is of short period during transfer of the charges.
In this case, if a drive circuit as used previously and as illustrated in FIG. 1 is employed in association with the frame transfer type CCD, then coupling capacitors C.sub.1 and C.sub.2 of extremely large capacitances have to be provided to maintain the state that any one of the transistors Q.sub.1 and Q.sub.2 is completely turned ON. This will not only make the drive circuit as described rather impractical, but will also make the integrated circuit fabrication of such a drive circuit very difficult.